1. Technical Field
The present disclosure relates to an image sensor, in particular of the CMOS type, such as those that equip digital still-photo cameras, digital video cameras, and mobile telephones. The present disclosure relates in particular to circuits to read and to amplify signals supplied by photosensitive elements of the image sensor.
2. Description of the Related Art
Conventionally, an image sensor of the CMOS type comprises pixel cells arranged in lines and in columns transversal to the lines. Each pixel cell is formed in a semiconductor substrate and comprises a photosensitive component such as a photodiode, associated with a read circuit. The read circuit comprises at least one transistor to transfer a charge accumulated in a charge accumulation region of the substrate where the photosensitive component is formed, which will hereinafter be called “sense node”, to a read node, and a transistor to reinitialize the read node to a certain charged value before proceeding with a new charge transfer from the sense node. The image sensor also comprises a control circuit and a processing circuit. In particular, the control circuit controls the shutter speed (electronic shutter). The processing circuit processes the signal from each pixel that is supplied by the read circuit.
FIG. 1 shows schematically an image sensor of the CMOS type. The image sensor conventionally comprises pixel cells arranged in lines and in columns transversal to the lines of pixels. For clarity reasons, only a single pixel cell PXL is shown in FIG. 1. The image sensor IS also comprises a pixel cell control circuit CTLC and a processing circuit PPC of the signal supplied by each pixel cell. The image sensor IS shown in FIG. 1 is of the four transistors per pixel cell type. Thus, each pixel cell PXL of the image sensor IS comprises four N-channel transistors T1, T2, T3, T4 and a photodiode PD of which an anode terminal is connected to ground. The transistor T1 comprises a source terminal connected to a cathode terminal of the photodiode PD and constituting a sense node SN, a drain terminal connected to a source terminal of the transistor T2 and constituting a read node RN, and a gate terminal receiving a read control signal RD. The transistor T2 comprises a drain terminal receiving a pixel supply voltage VPX and a gate terminal receiving a reset signal RST. The transistor T3 comprises a gate terminal connected to the read node RN, a drain terminal receiving the supply voltage VPX, and a source terminal connected to a drain terminal of the transistor T4. The transistor T4 comprises a gate terminal receiving a column selection signal LS and a source terminal supplying a pixel signal RS. Moreover, the gate of the transistor T1 and the gate of the transistor T2 of each of the pixel cells of a same pixel line receive respectively the same signal RD and the same signal RST. The gate of the transistor T4 of each of the pixel cells of a same pixel line receives a same signal LS. The source of the transistor T4 of each of the pixel cells of a same column of pixels is connected to a unique output supplying the pixel signal RS.
FIG. 2 shows timing diagrams of command signals RD, RST, and LS applied to each pixel cell PXL by the circuit CTLC during a read cycle. FIG. 2 also show charges accumulated at the sense node SN and at the read node RN at different moments. The nodes SN are RN are shown in the form of wells separated by a barrier 1 formed by the transistor T1.
The control of a pixel cell conventionally comprises four distinct moments t0, t1, t2, t3. Before moment t0, the electric charges accumulated by the photodiode PD at the sense node SN were transmitted to the read node RN upon the passage to 1 of the signal RD setting the transistor T1 in the conducting state, and the charges at node RN are evacuated to the supply source by setting the transistor T2 in the conducting state with the aid of the signal RST set at 1. Moment t0 occurs when the signal RD goes to 0, blocking the transistor T1, and when the sense node SN and read node RN are void of electrical charges. Moment t0 thus marks the beginning of an integration period (or exposition time) EXT during which the photodiode PD is exposed to the light and accumulates electrical charges at the sense node SN. Moment t1 marks the start of a read phase. This moment occurs when signal LS goes to 1, and is followed by a pulse P1 in the signal RST, allowing it to assure itself that the read node RN is void of all electrical charges. At moment t2, the pulse P1 is followed by a read of the voltage of the pixel signal RS supplying a reference voltage RFS corresponding to an absence of lighting of the diode PD. The voltage RFS is used to initialize an analog/digital converter of the circuit PPC, supplying digital samplings of an image signal. At moment t2, electrical charges have accumulated at the sense node SN since the start of the integration period EXT. Moment T2 is followed by a pulse P2 in the signal RD. The pulse P2 has the effect of making the transistor T1 conducting (removal of the barrier 1) and therefore to transfer the charges 2 accumulated at the node SN to the node RN. Moment t3 occurs after the emission of the pulse P2 and marks the moment of reading the voltage of the signal RS supplying a voltage PS corresponding to the electrical charges 2 present at node RN. Moment t3 is followed by a pulse P3 of the signal RST allowing all the charges found at the node RN to be evacuated to the supply, corresponding to moment t0.
Due to the increased miniaturization of image sensors and thus of the pixel cells, the charges susceptible of being accumulated by the photodiodes are weaker and weaker and saturation of the sense node happens with a lower and lower amount of exposition light. As a result, a reduction of the dynamic range of a pixel occurs, that is to say the range of light that a pixel of an image sensor is capable of discriminating. To avoid this inconvenience, and thus to increase the dynamic range of an image sensor of the CMOS type in certain lighting conditions of the image sensor, it has been proposed, in particular in the patent U.S. Pat. No. 7,586,523, to implement two integration periods and to read two pixel signals corresponding to these two integration periods in a wider dynamic mode.
The implementation of two integration periods is shown in FIG. 3, which shows timing diagrams of command signals RD, RST, and LS applied to each pixel cell PXL of FIG. 1. FIG. 3 also shows the charges accumulated at the sense node SN and read node RN at different moments during a read cycle of the pixel cell PXS.
In FIG. 3, the control of a pixel cell comprises seven successive distinct moments t0, t1, t2, t3, t4, t5, t6 in an increased dynamic mode. Before moment t0, the read node RN is initialized by evacuating the electrical charges accumulated at the node RN to the supply voltage VPX, by setting the transistor T2 in the conducting state, controlled by a pulse P5 of the signal RST. The electrical charges accumulated by the photodiode PD at the sense node SN are then transferred to the read node RN under the effect of a pulse P6 of the signal RD setting the transistor T1 in the conducting state. At moment t0, the signal RD goes to 0, blocking the transistor T1, and the sense node SN is void of electrical charges. Moment t0 thus marks the start of a long integration period TL during which the photodiode PD may accumulate under the effect of the light electrical charges 2a, 3a at the sense node SN. Moment t1 corresponds to the appearance of a pulse P7 in the signal RST. The pulse P7 controls the initialization of the read node RN. Moment t2 corresponds to the appearance of a pulse P8 in the signal RD. The pulse P8 has an intensity less than that of the pulse P6, for example on the order of half the intensity of the pulse P6, so as to partially lower the barrier 1 formed by the transistor T1, and to transfer only the electrical charges 3a exceeding a certain threshold MT from the sense node SN to the read node RN. The threshold MT is thus defined by the intensity of the pulse P8. The charges 3a are evacuated to the supply during a pulse P9 of the signal RST initializing the node RN, the pulse P9 being emitted before moment t3. The pulses P8 and P9 therefore allow for a performance of a skimming operation of the charges accumulated at the node SN. Moment t2 also marks the start of a short integration period TS. At moment t3, just after the pulse P9, a read of the voltage of the pixel signal RS is done to obtain a reference voltage SRF corresponding to an absence of lighting of the diode PD. The voltage SRF is used to initialize the analog/digital converter, which supplies digital samplings of the image signal, during the determination of a “short” pixel signal resulting from the short integration period TS. The read of the voltage SRF is followed by a pulse P10 of the signal RD having an intensity analogous to that of the pulse P8, allowing for the transfer of electrical charges 4a exceeding the threshold MT of the node SN to the node RN. Moment t4 follows the emission of the pulse P10 and marks the end of the short integration period TS and of the moment of reading the voltage of the signal RS supplying a “short” pixel signal SPS corresponding to the electrical charges 4a transferred to the node RN and accumulated during the short integration period TS. Moment t4 is followed by a pulse P11 of the signal RST at moment t5, allowing the charges 4a that may be found at node RN to be evacuated. Just after the pulse P11, a read of the voltage of the pixel signal RS is done to obtain a reference voltage LRF corresponding to an absence of lighting of the diode PD. The voltage LRF allows for the initialization of the analog/digital converter during the determination of a “long” pixel signal resulting from the long integration period TL. The reading of the voltage LRF is followed by a pulse P12 of the signal RD having an intensity analogous to that of the pulse P6, to transfer all the electrical charges present at the node SN to the node RN. Moment t6 follows the emission of the pulse P12 and marks the end of the long integration period TL and of the reading of the voltage of the signal RS supplying a “long” pixel signal LPS corresponding to the electrical charges 2a transferred to the node RN and accumulated during the long integration period TL.
The image sensor described in the patent U.S. Pat. No. 7,586,523 then supplies a pixel value having a wide dynamic range by applying the following formula:WDR=MAX(LS+SS×GA, SS×GA×R)  (1)wherein MAX(a , b) is a function supplying the largest number of values a and b, LS and SS are digitized samplings of the signals LPS and SPS, GA is a coefficient that may be equal to 1, and R=TL/TS is the ratio between the long integration TL and short integration TS durations.
FIG. 4 shows two variation curves C1, C2 of signals SS and WDR as a function of the lighting intensity of the diode PD. According to the curve C1, the signal SS becomes non-zero as from a certain value of lighting intensity corresponding to the threshold MT. The curve C1 thus presents a part that is substantially linear, linked by a curved part near a point PT1 to another linear part with a shallower slope. The curve C2 presents a first part that is substantially linear going from the origin of the reference point where the signal WDR is zero when the lighting of the diode PD is zero, until a point having a lighting intensity equal to L1 at the starting point of the curve C1. In this first part, the signal WDR is equal to the signal SL, the signal SS being zero. The curve C2 comprises a second part extending beyond the first part of the curve C2 and a point PT2, where the signal WDR is equal to SL+GA×SS for a lighting intensity L2, that is to say when the condition SL+GA×SS>GA×R×SS is met. The curve C2 comprises a third part extending beyond point PT2 where the signal WDR is equal to GA×R×SS, that is to say when the condition SL+GA×SS<GA×R×SS is met. At a certain distance from the point PT2, the first and third parts of the curve C2 have essentially identical slopes, corresponding to an operating zone that is substantially linear.
It so happens that the implementation of the formula (1) causes signal linearity problems near the point PT2 where the values LS+SS×GA and SS×GA×R are close, in particular due to the presence of the curved part of the curve C1 near point PT1. The difference between a straight line having the slope of the first and third parts and the curve C2 may therefore reach 12 to 15%. In the U.S. Pat. No. 7,586,523, it was attempted to reduce this non-linearity by adjusting the coefficient GA or by the use of several coefficients applied to the signal SS, depending on whether it is added to the signal SL or multiplied by the ratio R. However, these operations cause a deterioration of the resulting signal to noise ratio WDR without a significant reduction of the non-linearity.